Field of the Invention
The present invention relates to microelectronic packaging and elements thereof more specifically to an assembly for electrically interconnecting and packaging a plurality of microelectronic elements in a common package.
Description of the Related Art
Multi-chip packages which incorporate silicon interposers can be used to provide high speed, high bandwidth or a high degree of parallel interconnections between multiple microelectronic elements arranged side by side above a surface of a common interposer. Silicon interposers are typically formed from a relatively thick wafer in which wiring patterns and contacts are fabricated in a thin layer of the silicon wafer and above the thin layer, after which the bulk of the wafer is ground down or otherwise discarded. As silicon wafers are almost exclusively processed using semiconductor processing equipment in clean rooms, such processing and the discarding of the unneeded bulk wafer can make silicon interposers more expensive and more difficult to fabricate than other types of circuit structures.
In addition, the horizontal area of such multi-chip package can be large. A large size of a package can constrain further miniaturization of a system such as smart phone, tablet, phablet, other handheld device, personal computer or other computer in which the multi-chip package is incorporated.
For example, in an example of a multi-chip package 10 seen in FIG. 1, microelectronic elements 11, 12 and 14 overlie and are electrically interconnected with one another by silicon interposer 20 and are electrically interconnected with a substrate 30 through the silicon interposer 20. Electrical coupling of the silicon interposer with an underlying substrate 30 can be provided through electrically conductive features such as vias which formed typically by drilling through multiple levels of contacts and depositing a metal therein such as by electroless or electrolytic plating or, alternatively, physical or chemical vapor deposition processes.
Auxiliary components such as passive components 40, e.g., decoupling capacitors, and/or resistors can be electrically coupled to the substrate 30 outside the horizontal area of the silicon interposer 20, that is, beyond edges 22 of the silicon interposer. Such components 40 can cooperate with the microelectronic elements 11, 12, 14 of the assembly to provide improved function. As further seen in FIG. 1, a thermally conductive element, i.e., a heat spreader 50, can be thermally coupled to rear surfaces 52 of the microelectronic elements. The heat spreader may also serve as a protective cover for the assembly and the components 40 therein.
FIG. 2 further illustrates electrical and mechanical interconnection of the multi-chip package 10 within a system such as described above. For example, the multi-chip package 30 can be mounted on and electrically connected with a circuit panel 60 through solder balls 61. Clamps 70 may engage the package 10 at a foot portion 54 of the heat spreader and an outwardly facing surface 62 of the circuit panel 60. A further component 80 such as a housing, heat sink, cold plate, cooling duct, or fan can be thermally coupled to a surface 56 of the heat spreader which faces away from the microelectronic elements.
Further improvements in the structure and fabrication of the multi-chip package 10, as well as the horizontal area occupied thereby, would be desirable.
Size (or form factor as commonly quoted in the industry) is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
Semiconductor chips containing memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
As manufacturers of smartphones, tablets and other devices constantly seek increased performance and greater circuit density the trend for these devices is to provide ever greater functional capabilities in an amount of space on a circuit panel that may stay the same or decrease over time. In light of the foregoing, certain improvements can be made in the structure of microelectronic packages and assemblies which comprise a microelectronic package having a memory controller function, or “controller package” as further defined herein. Such improvements may help reduce the amount of space of a circuit panel, e.g., motherboard occupied by the controller and memory packages when such controller and memory packages are mounted in close proximity to one another at non-overlapping areas of the circuit panel.